The present application relates to a semiconductor structure and a method of forming the same. More particularly, the present application relates to a method of providing a semiconductor structure including a first array of semiconductor-containing pillar structures and a second array of semiconductor-containing pillar structures both of which extend upwards from a semiconductor substrate, wherein the various semiconductor-containing pillar structures have a higher lattice constant than the semiconductor substrate.
For more than three decades, the continued miniaturization of metal oxide semiconductor field effect transistors (MOSFETs) has driven the worldwide semiconductor industry. Various showstoppers to continued scaling have been predicated for decades, but a history of innovation has sustained Moore's Law in spite of many challenges. However, there are growing signs today that metal oxide semiconductor transistors are beginning to reach their traditional scaling limits. Since it has become increasingly difficult to improve MOSFETs and therefore complementary metal oxide semiconductor (CMOS) performance through continued scaling, further methods for improving performance in addition to scaling have become critical.
III-V compound semiconductor field effect transistors are considered a high performance option for future technology nodes. Co-integration of III-V semiconductor compounds with silicon is very challenging due to the high lattice mismatch between the III-V semiconductor compound and silicon. Such a challenge is not limited to the integration of III-V compound semiconductor with silicon, but also exists when integrating semiconductor materials having different lattice constants. Thus, a technique is needed to integrate semiconductor materials having different lattice constants.